Manufacturing method of semiconductor device

ABSTRACT

A semiconductor device includes: a chip mounting portion having a lower surface on which a first ditch is formed; a semiconductor chip mounted on an upper surface of the chip mounting portion; a lead electrically connected to a pad of the semiconductor chip through a conductive member; and a sealing body configured to seal the semiconductor chip, wherein the lower surface of the chip mounting portion is exposed from the sealing body, and wherein a plating film is formed on the lower surface including an inside of the first ditch.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation Application of U.S. patentapplication Ser. No. 15/548,077, filed on Aug. 1, 2017, which is a § 371National Stage of International Application No. PCT/JP2015/068179 filedon Jun. 24, 2015, the entire contents of which are hereby incorporatedby reference.

TECHNICAL FIELD

The present invention relates to a manufacturing technique of asemiconductor device, for example, a technique effectively applied to amanufacturing method of a semiconductor device having a structure inwhich a lower surface of a chip mounting portion is exposed from asealing body.

BACKGROUND ART

Japanese Unexamined Patent Application Publication No. 2014-7363 (PatentDocument 1) describes a technique of forming a single ditch on a lowersurface of a die pad exposed from a sealing body.

Japanese Unexamined Patent Application Publication No.

2012-94598 (Patent Document 2) describes a technique of removing resinburrs formed on a die pad exposed from a sealing body.

RELATED ART DOCUMENTS Patent Documents

-   Patent Document 1: Japanese Unexamined Patent Application    Publication No. 2014-7363-   Patent Document 2: Japanese Unexamined Patent Application    Publication No. 2012-94598

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

As a package configuration of a semiconductor device, there is a tabexposure type semiconductor device in which a lower surface of a chipmounting portion (die pad, tab) on which a semiconductor chip is mountedis exposed from a sealing body. This tab exposure type semiconductordevice has the advantage that heat generated in the semiconductor chipcan be efficiently radiated from the lower surface of the die padexposed from the sealing body.

However, the manufacturing process of the tab exposure typesemiconductor device includes a process of forming the sealing bodywhile exposing the lower surface of the chip mounting portion, and theresin constituting the sealing body inevitably leaks out on the lowersurface of the chip mounting portion in the actual process of formingthe sealing body. When this resin leakage increases, the region coveredwith the resin in the lower surface of the chip mounting portion becomeslarger, and there is a possibility that the heat radiation efficiencyfrom the exposed chip mounting portion decreases. Namely, even if thechip mounting portion is designed so that the lower surface thereof isexposed, since the resin leakage inevitably occurs in the actualmanufacturing process, how the resin leakage onto the lower surface ofthe chip mounting portion can be suppressed becomes important from theviewpoint of improving the heat radiation efficiency of thesemiconductor device. In other words, in order to manufacture asemiconductor device in which the lower surface of the chip mountingportion is exposed to improve heat radiation efficiency, it is necessaryto suppress the increase in the resin leakage that inevitably occurs inthe actual manufacturing process.

Other problems and novel features will become apparent from thedescription of this specification and the accompanying drawings.

Means for Solving the Problems

In a manufacturing method of a semiconductor device in one embodiment,when resin enters a first ditch formed on a lower surface of a chipmounting portion by a process of forming a sealing body made of theresin, the resin embedded in the first ditch is removed by a process ofcleaning the lower surface of the chip mounting portion, and a platingfilm is formed also on an inner wall of the first ditch in a process offorming the plating film on the lower surface of the chip mountingportion.

Effects of the Invention

According to one embodiment, the reliability of the semiconductor devicecan be improved.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a plan view of a chip mounting portion in a related techniqueviewed from the upper surface side;

FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;

FIG. 3 is a schematic cross-sectional view showing a state in which asealing body is formed by performing a sealing process with resin on thechip mounting portion in the related technique shown in FIG. 2;

FIG. 4A is a plan view of a semiconductor device in an embodiment viewedfrom the upper surface side, and FIG. 4B is a plan view of thesemiconductor device in the embodiment viewed from the bottom;

FIG. 5 is a plan view showing an inside of a sealing body seen throughthe sealing body in the semiconductor device of the embodiment;

FIG. 6 is a cross-sectional view of the semiconductor device in theembodiment taken along one section;

FIG. 7 is a partially enlarged view of a vicinity of a corner portion ofthe chip mounting portion viewed from the upper surface side;

FIG. 8 is a cross-sectional view taken along line A-A of FIG. 7;

FIG. 9 is a cross-sectional view showing a state in which thesemiconductor device in the embodiment is mounted on a mounting board;

FIG. 10 is a flowchart showing a flow of the manufacturing process ofthe semiconductor device in the embodiment;

FIG. 11 is a plan view showing the manufacturing process of thesemiconductor device in the embodiment;

FIG. 12A is a plan view and FIG. 12B is a cross-sectional view eachshowing the manufacturing process of the semiconductor device continuedfrom FIG. 11;

FIG. 13A is a plan view and FIG. 13B is a cross-sectional view eachshowing the manufacturing process of the semiconductor device continuedfrom FIGS. 12A and 12B;

FIG. 14A is a plan view and FIG. 14B is a cross-sectional view eachshowing the manufacturing process of the semiconductor device continuedfrom FIGS. 13A and 13B;

FIG. 15 is a cross-sectional view showing the manufacturing process ofthe semiconductor device continued from FIGS. 14A and 14B;

FIG. 16 is a cross-sectional view showing the manufacturing process ofthe semiconductor device continued from FIG. 15;

FIG. 17A is a plan view seen from the upper surface side and FIG. 17B isa plan view seen from the lower surface side each showing themanufacturing process of the semiconductor device continued from FIG.16;

FIG. 18 is a schematic diagram showing that the entry of resin issuppressed by a plurality of ditches formed on the lower surface of thechip mounting portion;

FIG. 19 is a cross-sectional view corresponding to the plan views shownin FIGS. 17A and 17B;

FIG. 20A is a plan view and FIG. 20B is a cross-sectional view eachshowing the manufacturing process of the semiconductor device continuedfrom FIGS. 19A and 19B;

FIG. 21A is a cross-sectional view showing the manufacturing process ofthe semiconductor device continued from FIG. 20, and FIG. 21B is apartially enlarged view of FIG. 21A;

FIG. 22 is a cross-sectional view showing the manufacturing process ofthe semiconductor device continued from FIGS. 21A and 21B;

FIG. 23A is a schematic diagram showing a first modification example,and FIG. 23B is a schematic diagram showing a second modificationexample;

FIG. 24A is a perspective view of a semiconductor device (individualmolding type) in a third modification example seen from the uppersurface side, and FIG. 24B is a perspective view of the semiconductordevice in the third modification example seen from the lower surfaceside;

FIG. 25 is a cross-sectional view showing the semiconductor device inthe third modification example;

FIG. 26A is a perspective view of a semiconductor device (batch moldingtype) in the third modification example seen from the upper surfaceside, and FIG. 26B is a perspective view of the semiconductor device inthe third modification example seen from the lower surface side; and

FIG. 27 is a cross-sectional view showing the semiconductor device inthe third modification example.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in aplurality of sections or embodiments when required as a matter ofconvenience. However, these sections or embodiments are not irrelevantto each other unless otherwise stated, and the one relates to the entireor a part of the other as a modification example, details, or asupplementary explanation thereof.

Also, in the embodiments described below, when referring to the numberof elements (including number of pieces, values, amount, range, and thelike), the number of the elements is not limited to a specific numberunless otherwise stated or except the case where the number isapparently limited to a specific number in principle, and the numberlarger or smaller than the specified number is also applicable.

Further, in the embodiments described below, it goes without saying thatthe components (including element steps) are not always indispensableunless otherwise stated or except the case where the components areapparently indispensable in principle.

Similarly, in the embodiments described below, when the shape of thecomponents, positional relation thereof, and the like are mentioned, thesubstantially approximate and similar shapes and the like are includedtherein unless otherwise stated or except the case where it isconceivable that they are apparently excluded in principle. The samegoes for the numerical value and the range described above.

Also, components having the same function are denoted by the samereference characters throughout the drawings for describing theembodiments, and the repetitive description thereof is omitted. Inaddition, hatching is used even in a plan view so as to make thedrawings easy to see.

Description of Related Technique

First, the related technique of the tab exposure type semiconductordevice will be described, and then improvements for the relatedtechnique will be studied. Thereafter, the technical idea made by thestudy of improvements for the related technique will be described. Itshould be noted that “related technique” referred to in thisspecification is a technique having a problem newly discovered by theinventor and is not a publicly known conventional technique, but is atechnique described with the intention for a prerequisite technique(unknown technique) of a novel technical idea.

A lead frame including a chip mounting portion and a lead is made of,for example, a copper material to be easily oxidized, and adhesiondecreases in the oxidized copper material. Therefore, in the tabexposure type semiconductor device, in order to improve connectionreliability when the semiconductor device is mounted on the mountingboard, a plating film that covers the exposed lower surface of the chipmounting portion is formed and the chip mounting portion is mounted onthe metal pattern (terminal) on the mounting board through this platingfilm. At this time, there are the case where the plating film to beformed on the lower surface of the chip mounting portion is formed on alead frame in advance and the case where the plating film is formed inthe manufacturing process of the semiconductor device.

In recent years, the plating film used for the semiconductor device hasbeen required to be lead-free from the viewpoint of environmentalconsideration. As the lead-free measures, in the related technique, forexample, a plating film comprised of a laminated film of Ni (nickel)/Pd(palladium)/Au (gold) is used, and the Ni/Pd/Au film is formed on thelead frame in advance.

Here, in the tab exposure type semiconductor device, the resinconstituting the sealing body inevitably leaks onto the lower surface ofthe chip mounting portion in the sealing process. Therefore, in the tabexposure type semiconductor device, it is conceivable that a cleaningprocess for removing the resin leaked onto the lower surface of the chipmounting portion is performed after the sealing process. However, in therelated technique, the cleaning process for removing the resin leakedonto the lower surface of the chip mounting portion is not performed.This is because when the cleaning process is performed in the relatedtechnique, nickel constituting the Ni/Pd/Au film piles up on the lowersurface of the chip mounting portion. In other words, this is becausewhen nickel piles up on the lower surface of the chip mounting portion,this nickel is easily oxidized, and thus the connection reliabilitybetween the chip mounting portion and the mounting board is lowered.

In other words, the Ni/Pd/Au film has a function of improving theconnection reliability between the chip mounting portion and themounting board by covering the chip mounting portion made of an easilyoxidized copper material. However, if the cleaning process for removingthe resin leaked onto the lower surface of the chip mounting portion isperformed, nickel piles up on the outermost surface of the Ni/Pd/Aufilm, and since this nickel is easily oxidized, even if the Ni/Pd/Aufilm is formed on the lower surface of the chip mounting portion, theconnection reliability between the chip mounting portion and themounting board cannot be improved. Namely, if the cleaning process forremoving the resin leaked onto the lower surface of the chip mountingportion is performed in the related technique, the function of theNi/Pd/Au film for improving the connection reliability disappears.

Therefore, it is difficult to perform the cleaning process in therelated technique from the viewpoint of improving the connectionreliability between the tab exposure type semiconductor device and themounting board. On the other hand, since the resin constituting thesealing body inevitably leaks onto the lower surface of the chipmounting portion in the sealing process, it is necessary to reduce theamount of resin leaked onto the lower surface of the chip mountingportion as much as possible in the related technique.

Specifically, FIG. 1 is a plan view of a chip mounting portion TAB in arelated technique viewed from the upper surface side. In FIG. 1, a stepportion DL is formed at the end of the chip mounting portion TAB, and aditch DIT is formed along the outer peripheral portion of the chipmounting portion TAB. Here, since the step portion DL and the ditch DITare formed on the lower surface of the chip mounting portion TAB, theyare indicated by broken lines in FIG. 1.

FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. Asshown in FIG. 2, the step portion DL is formed at the end of the lowersurface of the chip mounting portion TAB, and a single ditch DIT isformed on the inner side so as to be spaced apart from this step portionDL. Here, the thickness t1 of the chip mounting portion TAB, thedifference in level d1 of the step portion DL, and the depth d2 of theditch DIT are shown in FIG. 2.

FIG. 3 is a schematic cross-sectional view showing a state in which asealing body MR is formed by performing a sealing process with the resinRS on the chip mounting portion TAB in the related technique shown inFIG. 2. In FIG. 3, although the step portion DL is provided forsuppressing the spread of resin leakage on the lower surface of the chipmounting portion TAB, it is difficult to completely suppress the spreadof resin leakage only with the step portion DL. Therefore, in therelated technique, the ditch DIT is provided on the inner side so as tobe spaced apart from the step portion DL. Thus, the resin RS leaked ontothe lower surface of the chip mounting portion TAB enters the inside ofthe ditch DIT and is stopped. In this manner, according to the relatedtechnique, the spread of resin leakage to the region on the inner sideof the ditch DIT can be suppressed. In other words, in the relatedtechnique, the spread of resin RS leaked onto the lower surface of thechip mounting portion TAB is suppressed by providing the step portion DLand the ditch DIT. Accordingly, the ditch DIT provided in the relatedtechnique has a function of suppressing the spread of resin leakage tothe region on the inner side of the ditch DIT by causing the resin RS toenter the inside as much as possible. In other words, the basic idea ofproviding the ditch DIT in the related technique is to deepen the depthof the ditch DIT as much as possible to improve the function of stoppingthe spread of the resin RS with the ditch DIT. Namely, since the relatedtechnique is not based on the premise that the resin RS leaked onto thelower surface of the chip mounting portion TAB is removed, it naturallydoes not assume to remove the resin RS entering the inside of the ditchDIT. Therefore, in the related technique, the main focus is placed onimproving the function of stopping the spread of the resin RS with theditch DIT by increasing the depth of the ditch DIT as much as possiblewithout considering the ease of removing the resin RS embedded in theditch DIT. Accordingly, in the related technique, in order to enhancethe function of stopping the spread of the resin RS with the ditch DIT,for example, the depth d2 of the ditch DIT is set to ½ or more of thethickness t1 of the chip mounting portion TAB as shown in FIG. 2. Inaddition, in the related technique, the difference in level d1 of thestep portion DL is set to ½ or more of the thickness t1 of the chipmounting portion TAB.

In the related technique thus configured, as shown in FIG. 3, theplating film PF is exposed in the region A1 of the lower surface of thechip mounting portion TAB, whereas the area B1 of the lower surface ofthe chip mounting portion TAB is covered with the resin RS leaked ontothe lower surface of the chip mounting portion TAB. As a result, in therelated technique, since the heat radiation characteristics in theregion B1 covered with the resin RS deteriorate and the region B1 cannotbe used for connection with the mounting board, the connectionreliability between the chip mounting portion TAB and the mounting boardalso decreases. Namely, there is room for improvement in the relatedtechnique from the viewpoint of improving the heat radiationcharacteristics of the semiconductor device and improving the connectionreliability.

Thus, devises for overcoming the room for improvement existing in therelated technique are made in the present embodiment. Hereinafter, thedevised technical idea in the present embodiment will be described.

Basic Idea in Embodiment

In the basic idea in the present embodiment, on the premise that a ditchfor suppressing the spread of resin leakage is provided on the lowersurface of the chip mounting portion in the tab exposure typesemiconductor device, a cleaning process for removing the resin enteringthe inside of the ditch together with the resin leaked onto the lowersurface of the chip mounting portion is performed after the sealingprocess with the resin, and a plating film is formed also inside theditch after the cleaning process.

Namely, according to the basic idea of the present embodiment, whilesuppressing the spread of resin leakage with the ditch, the resinentering the inside of the ditch is removed, and a plating film isformed on the inner wall of the ditch. Thus, according to the basic ideain the present embodiment, the improvement in the heat radiationcharacteristics of the semiconductor device by removing the resin fromthe lower surface of the chip mounting portion including the inside ofthe ditch and the improvement in the connection reliability between thesemiconductor device and the mounting board by forming a plating filmalso on the inner wall of the ditch can be achieved.

The basic idea in the present embodiment is common to the relatedtechnique in that the ditch is provided on the lower surface of the chipmounting portion, but is different from the related technique in thatthe ditch provided in the present embodiment is based on the premisethat the resin entering the inside of the ditch is removed, whereas theditch provided in the related technique is not based on the premise thatthe resin entering the inside of the ditch is removed. In other words,the ditch in the present embodiment and the ditch provided in therelated technique are common in that both of the ditches have a functionof suppressing the spread of resin leakage on the lower surface of thechip mounting portion. However, since the design concept of the ditchprovided in the related technique is not based on the premise that theresin entering the inside of the ditch is removed, the design concepthas a basic idea specialized for increasing the internal volume of theditch as much as possible to improve the effect of stopping the spreadof the resin leakage. On the other hand, since the design concept of theditch provided in the present embodiment is based on a premise that theresin entering the inside of the ditch is removed, the design concepthas a basic idea in consideration of not only the function of stoppingthe spread of the resin leakage by the ditch but also the ease ofremoval of the resin entering the inside of the ditch. Thus, since thebasic idea in the present embodiment is different in the orientation(viewpoint) from the basic idea in the related technique, theconfiguration of the semiconductor device embodying the basic idea inthe present embodiment is different from the configuration of thesemiconductor device in the related technique. In other words, the lowersurface configuration of the chip mounting portion in the presentembodiment is different from the lower surface configuration of the chipmounting portion in the related technique.

<Configuration of Semiconductor Device>

In the following, the configuration of the semiconductor device in thepresent embodiment will be described.

FIGS. 4A and 4B are plan views each showing the configuration of thesemiconductor device PKG1 in the present embodiment. In particular, FIG.4A is a plan view of the semiconductor device PKG1 in the presentembodiment viewed from the upper surface side (front side), and FIG. 4Bis a plan view of the semiconductor device PKG1 in the presentembodiment viewed from the lower surface side (back side). In FIG. 4A,the semiconductor device PKG1 in the present embodiment includes, forexample, a sealing body MR having a rectangular shape, and a pluralityof leads LD protrude from four sides of the sealing body MR. On theother hand, in FIG. 4B, in the semiconductor device PKG1 in the presentembodiment, the lower surface of the chip mounting portion TAB isexposed from the sealing body MR, and double ditches DIT1 and DIT2 areformed along the outer peripheral portion of the chip mounting portionTAB in the exposed chip mounting portion TAB. As described above, thesemiconductor device PKG1 in the present embodiment constitutes aso-called tab exposure type semiconductor device, in which the lowersurface of the chip mounting portion TAB is exposed from the sealingbody MR, and in particular, the package structure of the semiconductordevice PKG1 in the present embodiment is a Quad Flat Package (QFP).

Next, FIG. 5 is a plan view showing an inside of the sealing body MRseen through the sealing body in the semiconductor device PKG1 of thepresent embodiment. As shown in FIG. 5, the rectangular-shaped chipmounting portion TAB is arranged in the central part of the inside ofthe sealing body MR, and the rectangular-shaped semiconductor chip CHPis mounted on the upper surface of the chip mounting portion TAB. Forexample, an integrated circuit is formed in the semiconductor chip CHP,the integrated circuit includes a plurality of field effect transistorsformed on a semiconductor substrate and multilayer wiring formed abovethe field effect transistors, and a plurality of pads PD shown in FIG. 5are formed in the uppermost layer of the multilayer wiring. For example,the plurality of pads PD are arranged along the outer peripheral portionof the rectangular-shaped semiconductor chip CHP, and the pad PD formedon the semiconductor chip CHP and the lead LD are electrically connectedby, for example, a wire made of gold wire (conductive member) W.

Subsequently, FIG. 6 is a cross-sectional view of the semiconductordevice PKG1 in the present embodiment taken along a section. As shown inFIG. 6, the semiconductor device PKG1 in the present embodiment includesthe sealing body MR made of, for example, resin and the lower surface ofthe chip mounting portion TAB is exposed from the sealing body MR.Further, the semiconductor chip CHP is mounted on the upper surface ofthe chip mounting portion TAB, and the pad formed on the surface of thesemiconductor chip CHP (not shown in FIG. 6) and the lead LD areconnected by the wire W. Here, in the present embodiment, on the lowersurface of the chip mounting portion TAB exposed from the sealing bodyMR, the step portion DL is formed at the outer edge (outer end), theditch DIT1 is formed on the inner side of the step portion DL, and theditch DIT2 is formed on the inner side of the ditch DIT1. In this case,in the semiconductor device PKG1 in the present embodiment, the resinconstituting the sealing body MR is embedded in the step portion DL,while no resin is formed inside the ditch DIT1 and the ditch DIT2.

FIG. 7 is a partially enlarged view of the vicinity of a corner portionof the chip mounting portion TAB viewed from the upper surface side. InFIG. 7, it can be seen that the step portion DL is formed on the lowersurface of the chip mounting portion TAB, the ditch DIT1 is formed onthe inner side of this step portion DL, and the ditch DIT2 is formed onthe inner side of the ditch DIT1. Further, as shown in FIG. 7, the ditchDIT1 and the ditch DIT2 are formed along the outer peripheral portion ofthe chip mounting portion TAB, and in particular, the ditch DIT1 and theditch DIT2 are formed in a tapered shape in the vicinity of the cornerportion of the chip mounting portion TAB.

Next, FIG. 8 is a cross-sectional view taken along line A-A of FIG. 7.As shown in FIG. 8, the lower surface of the chip mounting portion TABis exposed from the sealing body MR made of the resin RS, and the stepportion DL, the ditch DIT1, and the ditch DIT2 are formed on the exposedlower surface of the chip mounting portion TAB. In this case, the insideof the step portion DL is filled with the resin RS, while the resin RSis not formed and the plating film PF is formed inside the ditch DIT1and the ditch DIT2. Namely, on the lower surface of the chip mountingportion TAB, the plating film PF is formed over the region A2 shown inFIG. 8. Here, in the present embodiment, as the relationship between thethickness t1 of the chip mounting portion TAB, the difference in leveld1 of the step portion DL, and the depth d2 of the ditch DIT1 and theditch DIT2, the relationships of d1≤½×t1 and d2≤½×t1 hold as shown inFIG. 8. In addition, in the present embodiment, the distance L1 betweenthe step portion DL and the central part of the ditch DIT1 and thedistance L2 between the central part of the ditch DIT1 and the centralpart of the ditch DIT2 have the relationship of L1<L2 as shown in FIG.8.

The semiconductor device in the present embodiment is configured asdescribed above, and further detailed configuration thereof issummarized as follows.

(1) The semiconductor device PKG1 in the present embodiment includes thechip mounting portion TAB having the lower surface on which the ditchDIT1 is formed, the semiconductor chip CHP mounted on the upper surfaceof the chip mounting portion TAB, the lead LD electrically connected tothe pad PD of the semiconductor chip CHP through the wire W, and thesealing body MR for sealing the semiconductor chip CHP. Further, thelower surface of the chip mounting portion TAB is exposed from thesealing body MR and the plating film PF is formed on the lower surfaceincluding the inside of the ditch DIT1.

(2) In the ditch DIT1, the resin RS constituting the sealing body MR isnot formed.

(3) The ditch DIT1 is formed along the outer peripheral portion of thechip mounting portion TAB.

(4) The depth d2 of the ditch DIT1 is ½ or less of the thickness t1 ofthe chip mounting portion TAB.

(5) The cross-sectional shape of the ditch DIT1 is V-shape.

(6) On the lower surface of the chip mounting portion TAB, the ditchDIT2 is further formed so as to be spaced apart from the ditch DIT1.

(7) The ditch DIT2 is formed on the inner side of the chip mountingportion TAB relative to the ditch DIT1.

(8) The depth d2 of the ditch DIT1 and the depth d2 of the ditch DIT2are both ½ or less of the thickness t1 of the chip mounting portion TAB.

(9) The plating film PF is formed also on the inner wall of the ditchDIT2.

(10) In the ditch DIT2, the resin RS constituting the sealing body MR isnot formed.

(11) At the outer end of the lower surface of the chip mounting portionTAB, the step portion DL spaced apart from the ditch DIT1 is formed.

(12) The ditch DIT1 is formed on the inner side of the step portion DL.

(13) The depth d2 of the ditch DIT1 is shallower than the difference inlevel d1 of the step portion DL.

(14) The ditch DIT2 is formed on the inner side of the ditch DIT1 on thelower surface of the chip mounting portion TAB, and the distance L1between the step portion DL and the center position of the ditch DIT1 issmaller than the distance L2 between the center position of the ditchDIT1 and the center position of the ditch DIT2 in a cross-sectionalview.

(15) The resin RS constituting the sealing body MR is formed inside thestep portion DL.

(16) The chip mounting portion TAB has a first side extending in thefirst direction, a second side crossing the first side, and a cornerportion which is the intersection of the first side and the second side.Further, the ditch DIT1 includes a first portion parallel to the firstside, a second portion parallel to the second side, and a third portionconnecting the first portion and the second portion. In this case, thedistance between the third portion of the ditch DIT1 and the cornerportion is longer than the distance between the first portion of theditch DIT1 and the first side, and is longer than the distance betweenthe second portion of the ditch DIT1 and the second side.

(17) The angle formed by the third portion and the first portion of theditch DIT1 is an obtuse angle, and the angle formed by the third portionand the second portion of the ditch DIT1 is an obtuse angle.

Next, the state where the semiconductor device PKG1 in the presentembodiment is mounted on the mounting board MB will be described. FIG. 9is a cross-sectional view showing a state where the semiconductor devicePKG1 in the present embodiment is mounted on the mounting board MB. InFIG. 9, a terminal TE1 and a terminal TE2 are formed on the uppersurface of the mounting board MB, and the semiconductor device PKG1 inthe present embodiment is mounted on the upper surface of the mountingboard MB. Specifically, as shown in FIG. 9, the lower surface of thechip mounting portion TAB exposed from the sealing body MR and theterminal TE2 of the mounting board MB are electrically connected by thesolder material SL, and a part of the lead LD protruding from thesealing body MR (outer lead) and the terminal TE1 of the mounting boardMB are electrically connected by the solder material SL. In this manner,the semiconductor device PKG1 in the present embodiment is mounted onthe mounting board MB.

Structural Feature in Embodiment

Subsequently, the structural feature in the present embodiment will bedescribed. For example, the structural feature in the present embodimentis that the resin RS is not formed inside the ditch DIT1 and inside theditch DIT2 and the plating film PF is formed over the inner wall of theditch DIT1 and the inner wall of the ditch DIT2 as shown in FIG. 8. Inother words, the structural feature in the present embodiment is thatthe plating film PF is formed over the region A2 including the ditchDIT1 and the ditch DIT2 in the lower surface of the chip mountingportion TAB as shown in FIG. 8.

Thus, as shown in FIG. 9, the entire region including the ditch DIT1 andthe ditch DIT2 (region A2 in FIG. 8) can be used for the electricalconnection with the terminal TE2 of the mounting board MB. Therefore,according to the present embodiment, the connection reliability betweenthe semiconductor device PKG1 and the mounting board MB can be improved.Furthermore, since the ditch DIT1 and the ditch DIT2 can be brought intocontact with the terminal TE2 of the mounting board MB through theplating film PF, the heat radiation efficiency from the chip mountingportion TAB can be improved. Namely, according to the presentembodiment, since the entire region A2 including the ditch DIT1 and theditch DIT2 can be used as the heat radiation path, the heat generated inthe semiconductor chip CHP can be radiated efficiently from the lowersurface of the chip mounting portion TAB. Thus, according to the presentembodiment, not only the connection reliability between thesemiconductor device PKG1 and the mounting board MB can be improved, butthe suppression of the malfunction of the semiconductor device PKG1 canbe achieved by the improvement in the heat radiation efficiency, so thatthe reliability of the semiconductor device PKG1 can be greatly improvedby the synergy effect thereof.

For example, in the related technique, the resin RS remains inside theditch DIT, the plating film PF is not formed on the inner wall of theditch DIT, and the resin RS is formed in the region B1 including theditch DIT in the lower surface of the chip mounting portion TAB as shownin FIG. 3. Therefore, in the related technique, the region B1 cannot beused for the connection with the mounting board, and only the region A1on the inner side of the ditch DIT can be used for the connection withthe mounting board. Accordingly, since the contact area of theconductive member (plating film PF) between the semiconductor device andthe mounting board is small in the related technique, the connectionreliability between the chip mounting portion TAB and the mounting boarddecreases, and since the region contributing to the increase in the heatradiation efficiency also decreases, the heat radiation efficiency alsodecreases. As a result, according to the related technique, since theresin RS remains inside the ditch DIT, the connection reliabilitybetween the semiconductor device and the mounting board decreases andthe heat radiation efficiency from the semiconductor device decreases,so that the reliability of the semiconductor device in the relatedtechnique decreases due to the synergy effect thereof.

On the other hand, according to the semiconductor device PKG1 in thepresent embodiment, the resin RS is not formed inside the ditch DIT1 andinside the ditch DIT2, and the plating film PF is formed therein asshown in FIG. 8. Thus, according to the present embodiment, theformation region of the ditch DIT1 and the ditch DIT2 can also be usedfor the connection with the mounting board MB. Further, since the regionA2 including the ditch DIT1 and the ditch DIT2 is wider than the regionA1 in the related technique, the connection area between thesemiconductor device PKG1 and the mounting board MB can be increased inthe semiconductor device PKG1 in the present embodiment as compared tothat in the related technique. As a result, according to the presentembodiment, the connection reliability between the semiconductor devicePKG1 and the mounting board MB can be improved, and the heat radiationefficiency from the semiconductor device PKG1 can be improved ascompared to the related technique. Therefore, according to the presentembodiment, the reliability of the semiconductor device can be improvedas compared to the related technique.

<Manufacturing Method of Semiconductor Device>

The semiconductor device PKG1 in the present embodiment is configured asdescribed above, and the manufacturing method thereof will be describedbelow with reference to the drawings.

First, FIG. 10 is a flowchart showing the flow of the manufacturingprocess of the semiconductor device in the present embodiment, and theflow of the manufacturing process of the semiconductor device in thepresent embodiment will be briefly described based on this flowchart. InFIG. 10, for example, a lead frame including a lead and a chip mountingportion is prepared (S101). At this time, the step portion and ditch areformed in advance on the lower surface of the chip mounting portion ofthe prepared lead frame.

Next, a semiconductor chip is mounted on the chip mounting portion ofthe lead frame (chip mounting process) (S102). Thereafter, the padformed on the surface of the semiconductor chip and the lead provided onthe lead frame are electrically connected by a conductive member (wire)(wire bonding process) (S103). Subsequently, a sealing body made ofresin is formed so as to cover the semiconductor chip and a part of thelead (inner lead part) and expose the lower surface of the chip mountingportion (molding process) (S104). Then, the lower surface of the chipmounting portion is cleaned (cleaning process) (S105). At this time, ifthe resin leaked onto the lower surface of the chip mounting portionexists, the resin is removed from the lower surface of the chip mountingportion by this cleaning process.

Thereafter, a plating film is formed on the lower surface of the chipmounting portion exposed from the sealing body and the other part of thelead (outer lead part) (plating process) (S106). Next, after shaping thelead (shaping process) (S107), the semiconductor device is diced intopieces (dicing process) (S108). In this manner, the semiconductor devicein the present embodiment can be manufactured. The manufacturedsemiconductor device is mounted on, for example, a mounting board(mounting process) (S109). Specifically, the lower surface of the chipmounting portion exposed from the sealing body and the terminal of themounting board are connected through the solder material, and the leadpart exposed from the sealing body and the terminal of the mountingboard are connected through the solder material. In the manner describedabove, the tab exposure type semiconductor device is mounted on themounting board.

Subsequently, the manufacturing process of the semiconductor device inthe present embodiment will be further described with reference to thedrawings. First, as shown in FIG. 11, a lead frame LF in which productregions PR are arranged in an array is prepared. Here, FIG. 12A is anenlarged plan view showing the product region PR, and FIG. 12B is across-sectional view showing one section of the product region PR. Asshown in FIG. 12A, the rectangular chip mounting portion TAB is arrangedin the central part of the product region PR, and the plurality of leadsLD are arranged around the chip mounting portion TAB. In addition, asshown in FIG. 12B, on the lower surface of the chip mounting portionTAB, the step portion DL, the ditch DIT1, and the ditch DIT2 are formedin advance so as to be spaced apart from each other. Specifically, theditch DIT1 is formed on the inner side of the step portion DL, and theditch DIT2 is formed on the inner side of the ditch DIT1. Further, thedepth of the ditch DIT1 and the depth of the ditch DIT2 are shallowerthan the difference in level of the step portion DL. In addition, thedistance between the step portion DL and the center position of theditch DIT1 is smaller than the distance between the center position ofthe ditch DIT1 and the center position of the ditch DIT2 in across-sectional view.

In this case, the step portion DL, the ditch DIT1, and the ditch DIT2are formed by, for example, a press method, and a vertical step isformed in the step portion DL, while the cross-sectional shape of theditch DIT1 and the ditch DIT2 is V-shape.

Furthermore, as shown in FIG. 12B, the arrangement position of the leadLD is higher than the arrangement position of the chip mounting portionTAB. In other words, the arrangement position of the chip mountingportion TAB is lower than the arrangement position of the lead LD.

Next, the semiconductor chip CHP having a pad formed on the surfacethereof is prepared. Then, as shown in FIGS. 13A and 13B, thesemiconductor chip CHP is mounted on the upper surface of the chipmounting portion TAB. Thereafter, as shown in FIGS. 14A and 14B, the padformed on the semiconductor chip CHP and the lead LD are electricallyconnected by the wire W.

Subsequently, as shown in FIG. 15, the lead frame is sandwiched betweenthe lower mold BM and the upper mold UM while forming the cavity CAV.Specifically, the chip mounting portion TAB on which the semiconductorchip CHP is mounted is disposed on the lower mold BM, and the lead LD issandwiched between the lower mold BM and the upper mold UM. Thus, thechip mounting portion TAB on which the semiconductor chip CHP is mountedis disposed in the cavity CAV sealed by the lower mold BM and the uppermold UM. In this state, as shown in FIG. 16, the resin RS is injectedinto the cavity CAV hermetically sealed by the lower mold BM and theupper mold UM. At this time, since the step portion DL is formed at theouter end of the chip mounting portion TAB in the present embodiment,the injection pressure by the resin RS injected from the side face ofthe chip mounting portion TAB is dispersed as shown in FIG. 16. As aresult, the resin RS hardly intrudes below the lower surface of the chipmounting portion TAB disposed on the lower mold BM. Namely, in thepresent embodiment, the step portion DL formed at the outer end of thechip mounting portion TAB has a function of dispersing the injectionpressure by the resin RS to suppress the resin RS from entering thelower surface of the chip mounting portion TAB. In the manner describedabove, the process of sealing the semiconductor chip CHP with the resinRS can be performed while exposing a part of the lead LD and the lowersurface of the chip mounting portion TAB.

As described above, in the present embodiment, the step portion DL isprovided at the outer end of the chip mounting portion TAB in order tosuppress the resin RS from entering the lower surface of the chipmounting portion TAB, but it is difficult to reliably suppress the resinRS from entering the lower surface of the chip mounting portion TABsimply by providing the step portion DL. In other words, in the processof sealing the semiconductor chip CHP with the resin RS while exposingthe lower surface of the chip mounting portion TAB, even if the stepportion DL for preventing the leakage of the resin RS is provided, theresin RS may enter the lower surface of the chip mounting portion TAB.

Specifically, FIGS. 17A and 17B are diagrams showing the state afterforming the sealing body MR made of the resin RS in the product regionPR of the lead frame. In particular, FIG. 17A is a plan view of thesealing body MR seen from the upper surface side, and FIG. 17B is a planview of the sealing body MR seen from the lower surface side.

As shown in FIG. 17B, the lower surface of the chip mounting portion TABis exposed from the lower surface of the sealing body MR, and FIG. 17Bshows the case where the resin RS enters the lower surface of the chipmounting portion TAB. As shown in FIG. 17B, it can be seen that theditch DIT1 and the ditch DIT2 spaced apart from each other are formedalong the outer peripheral portion of the chip mounting portion TAB onthe lower surface of the chip mounting portion TAB. In other words, theditch DIT1 is formed on the outside along the outer peripheral portionof the chip mounting portion TAB, and the ditch DIT2 is formed on theinner side of the ditch DIT1.

Here, although the resin RS enters the lower surface of the chipmounting portion TAB as shown in FIG. 17B, it can be seen that the resinRS is stopped by the ditch DIT1 and the ditch DIT2 formed on the lowersurface of the chip mounting portion TAB, and the resin RS does notenter the region on the inner side of the ditch DIT2. Namely, it can beseen that since the ditch DIT1 and the ditch DIT2 are provided on theinner side of the step portion DL on the lower surface of the chipmounting portion TAB in the present embodiment, the entry of the resinRS which cannot be prevented by the step portion DL is stopped by theditch DIT1 and the ditch DIT2. In other words, it can be seen that evenif the resin RS enters the lower surface of the chip mounting portionTAB, since the ditch DIT1 and the ditch DIT2 are provided on the innerside of the step portion DL according to the present embodiment, theentry of the resin RS into the inner region of the ditch DIT2 on theinner side is suppressed.

Specifically, FIG. 18 is a schematic diagram showing that the entry ofthe resin RS is suppressed by the ditch DIT1 and the ditch DIT2 formedon the lower surface of the chip mounting portion TAB. In particular, asshown in FIG. 18, it can be seen that the entry of the resin RS into theinner region of the ditch DIT2 is suppressed in the present embodiment.At this time, as is apparent from FIG. 18, when the resin RS enters boththe ditch DIT1 and the ditch DIT2 formed on the lower surface of thechip mounting portion TAB, the amount of the resin RS entering the ditchDIT1 is larger than the amount of the resin RS entering the ditch DIT2.In other words, the entry of the resin RS is first suppressed by theditch DIT1 formed on the outside, and the resin RS that is not stoppedby the ditch DIT1 is stopped by the ditch DIT2 formed on the inside.Accordingly, as shown in FIG. 18, the amount of the resin RS enteringthe ditch DIT1 is larger than the amount of the resin RS entering theditch DIT2.

As described above, the process of sealing the semiconductor chip CHPwith the resin RS can be performed while exposing a part of the lead LDand the lower surface of the chip mounting portion TAB. FIG. 19 shows astate where the resin RS is embedded in the ditch DIT1 and the ditchDIT2 formed on the lower surface of the chip mounting portion TAB atthis time. Next, as shown in FIGS. 20A and 20B, the lower surface of thechip mounting portion TAB is cleaned. This removes the resin RS embeddedin the ditch DIT1 and the ditch DIT2. For example, the process ofcleaning the lower surface of the chip mounting portion TAB can beperformed by a combination of electrolytic deburring (electrolysis) andhydraulic deburring (high pressure water jet). Namely, in the cleaningprocess in the present embodiment, the attached resin RS is floated bythe electrolytic deburring, and then the floated resin RS is blown awayand removed by the hydraulic deburring.

Subsequently, as shown in FIGS. 21A and 21B, the plating film PF isformed on a part of the lead LD exposed from the sealing body MR and thelower surface of the chip mounting portion TAB exposed from the sealingbody MR. Specifically, in the exterior plating process in the presentembodiment, the plating film PF made of pure tin (Sn) is formed by, forexample, an electrolytic plating method. It should be noted that it isonly required to form the plating film PF from a material containing nolead (lead-free material), and a material made of tin-bismuth ortin-copper may be used in addition to pure tin.

From the foregoing, in the present embodiment, when the resin RS entersthe ditch DIT1 and the ditch DIT2 formed on the lower surface of thechip mounting portion TAB by the process of forming the sealing body MR(see FIG. 18), the resin RS embedded in the ditch DIT1 and the ditchDIT2 is removed by the cleaning process (see FIG. 20). Then, in theexterior plating process, the plating film PF is formed also on theinner wall of the ditch DIT1 and the inner wall of the ditch DIT2 (seeFIGS. 21A and 21B).

Thereafter, as shown in FIG. 22, for example, the lead LD protrudingfrom the sealing body MR is formed into a gull-wing shape, and then thesemiconductor device PKG1 is diced into pieces. In the manner describedabove, the semiconductor device PKG1 in the present embodiment can bemanufactured.

Feature Including Manufacturing Method in Embodiment

In the basic idea in the present embodiment, on the premise that a ditchfor suppressing the spread of resin leakage is provided on the lowersurface of the chip mounting portion in the tab exposure typesemiconductor device, a cleaning process for removing the resin enteringthe inside of the ditch together with the resin leaked onto the lowersurface of the chip mounting portion is performed after the sealingprocess with the resin, and a plating film is formed also inside theditch after the cleaning process.

Further, the present embodiment has features embodying the basic ideadescribed above, and the features including the manufacturing method inthe present embodiment will be described below.

The first feature in the present embodiment is that the plating film PFis not formed in advance in the prepared lead frame LF, but is formed inthe manufacturing process of the semiconductor device. In addition, thefirst feature in the present embodiment is that the plating film PF isformed on the lower surface of the chip mounting portion TAB in theprocess after the process of cleaning the lower surface of the chipmounting portion TAB exposed from the sealing body MR is performed asshown in FIGS. 20 and 21. In this manner, according to the presentembodiment, the plating film PF can be formed on the inner wall of theditch DIT1 and the inner wall of the ditch

DIT2 as shown in FIG. 21B. In other words, according to the firstfeature in the present embodiment, when the resin RS enters the ditchDIT1 and the ditch DIT2 formed on the lower surface of the chip mountingportion TAB by the process of forming the sealing body MR, the resin RSembedded in the ditch DIT1 and the ditch DIT2 is removed by the processof cleaning the lower surface of the chip mounting portion TAB. Further,in the exterior plating process, the plating film PF can be formed alsoon the inner wall of the ditch DIT1 and the inner wall of the ditchDIT2. As a result, according to the present embodiment, for example, theentire region including the ditch DIT1 and the ditch DIT2 (region A2 inFIG. 8) can be used for electrical connection with the terminal TE2 ofthe mounting board MB as shown in FIG. 9. Therefore, according to thepresent embodiment, the connection reliability between the semiconductordevice PKG1 and the mounting board MB can be improved. Furthermore,since the ditch DIT1 and the ditch DIT2 can be brought into contact withthe terminal TE2 of the mounting board MB through the plating film PF,the heat radiation efficiency from the chip mounting portion TAB can beimproved. Namely, according to the present embodiment, since the regionincluding the ditch DIT1 and the ditch DIT2 can be used as the heatradiation path, the heat generated in the semiconductor chip CHP can beradiated efficiently from the lower surface of the chip mounting portionTAB. Therefore, according to the present embodiment, not only theconnection reliability between the semiconductor device PKG1 and themounting board MB can be improved, but the suppression of themalfunction of the semiconductor device PKG1 can be achieved by theimprovement in the heat radiation efficiency, so that the reliability ofthe semiconductor device PKG1 can be improved by the synergy effectthereof.

For example, in the related technique, as the lead-free measures, theplating film PF comprised of a laminated film of Ni (nickel)/Pd(palladium)/Au (gold) is used, and a Ni/Pd/Au film is formed on the leadframe in advance. However, in the related technique thus configured, itis difficult to perform the cleaning process for removing the resin RSleaked onto the lower surface of the chip mounting portion TAB. This isbecause since the plating film PF is formed on the lead frame LF inadvance in the related technique, it is inevitable that the plating filmPF is adversely affected by performing the cleaning process in therelated technique. Specifically, in the related technique, when thecleaning process is performed, nickel constituting the Ni/Pd/Au filmpiles up on the lower surface of the chip mounting portion TAB. Then,when nickel piles up on the lower surface of the chip mounting portionTAB, since this nickel is easily oxidized, the connection reliabilitybetween the chip mounting portion TAB and the mounting board MB islowered. Therefore, in the related technique, it is difficult to performthe cleaning process for removing the resin RS leaked onto the lowersurface of the chip mounting portion TAB.

On the other hand, according to the present embodiment, the plating filmPF made of, for example, pure tin is formed in the manufacturing processof the semiconductor device (exterior plating process) instead offorming the plating film PF comprised of a laminated film of Ni(nickel)/Pd (palladium)/Au (gold) on the prepared lead frame LF inadvance as in the related technique. Thus, according to the presentembodiment, the sealing body MR is formed in the process before theexterior plating process, and the process of cleaning the lower surfaceof the chip mounting portion TAB can be inserted between the process offorming the sealing body MR and the exterior plating process. This isbecause since the exterior plating process is performed after thecleaning process is performed according to this configuration, thecleaning process does not affect the plating film PF.

From the foregoing, the first feature in the present embodiment is thatthe plating film PF made of a lead-free material is formed in themanufacturing process of the semiconductor device. In addition, thefirst feature in the present embodiment is that the exterior platingprocess for forming the plating film PF is performed in the processafter the process of forming the sealing body MR. Further, the firstfeature makes it possible to insert the process of cleaning the lowersurface of the chip mounting portion TAB in the process before theexterior plating process. As a result, according to the presentembodiment, even when the resin RS also enters the ditch DIT1 and theditch DIT2 formed on the lower surface of the chip mounting portion TAB,the resin RS embedded in the ditch DIT1 and the ditch DIT2 is removed bythe process of cleaning the lower surface of the chip mounting portionTAB, and the plating film PF is formed also on the inner wall of theditch DIT1 and the inner wall of the ditch DIT2 in the exterior platingprocess. As a result, the inside of the ditch DIT1 and the inside of theditch DIT2 also contribute to the connection between the semiconductordevice PKG1 and the mounting board MB, so that the connectionreliability between the semiconductor device PKG1 and the mounting boardMB can be improved and the heat radiation characteristics of thesemiconductor device PKG1 can be improved according to the presentembodiment.

The basic idea in the present embodiment is common to the relatedtechnique in that the ditch is provided on the lower surface of the chipmounting portion, but is different from the related technique in thatthe ditch provided in the present embodiment is based on the premisethat the resin entering the inside of the ditch is removed, whereas theditch provided in the related technique is not based on the premise thatthe resin entering the inside of the ditch is removed. In other words,the ditch in the present embodiment and the ditch provided in therelated technique are common in that both of the ditches have a functionof suppressing the spread of resin leakage on the lower surface of thechip mounting portion. However, since the design concept of the ditchprovided in the related technique is not based on the premise that theresin entering the inside of the ditch is removed, the design concepthas a basic idea specialized for increasing the internal volume of theditch as much as possible to improve the effect of stopping the spreadof the resin leakage. On the other hand, since the design concept of theditch provided in the present embodiment is based on a premise that theresin entering the inside of the ditch is removed, the design concepthas a basic idea in consideration of not only the function of stoppingthe spread of the resin leakage with the ditch but also the ease ofremoval of the resin entering the inside of the ditch. Thus, since thebasic idea in the present embodiment is different in the orientation(viewpoint) from the basic idea in the related technique, theconfiguration of the semiconductor device embodying the basic idea inthe present embodiment is different from the configuration of thesemiconductor device in the related technique. In other words, the lowersurface configuration of the chip mounting portion in the presentembodiment is different from the lower surface configuration of the chipmounting portion in the related technique.

In the following, the second feature in the present embodiment embodyingthis basic idea will be described. The second feature in the presentembodiment is that the shape of the ditch DIT1 and the shape of theditch DIT2 are devised in order to easily remove the resin RS enteringthe inside of the ditch DIT1 and the inside of the ditch DIT2.Specifically, as shown in FIG. 8, the ditch DIT1 and the ditch DIT2 areconfigured so that each of the depth d2 of the ditch DIT1 and the depthd2 of the ditch DIT2 is ½ or less of the thickness t1 of the chipmounting portion TAB. In this manner, according to the presentembodiment, the depth d2 of the ditch DIT1 and the depth d2 of the ditchDIT2 can be made shallower. This means that the resin RS entering theinside of the ditch DIT1 and the ditch DIT2 can be easily removed. As aresult, according to the second feature in the present embodiment, theresin RS entering the ditch DIT1 and the ditch DIT2 can be reliablyremoved by the cleaning process for cleaning the lower surface of thechip mounting portion TAB. In this regard, in the related technique, forexample, the depth of the ditch DIT is greater than ½ of the thicknessof the chip mounting portion TAB as shown in FIG. 3. This is becausesince the related technique is not based on the premise that the resinRS entering the inside of the ditch DIT is removed, the focus is placedonly on improving the effect of stopping the spread of the resin leakageby increasing the internal volume of the ditch DIT as much as possible.On the other hand, since the ditch DIT1 (ditch DIT2) provided in thepresent embodiment is based on the premise that the resin RS enteringthe inside of the ditch DIT1 (ditch DIT2) is removed, the ditch DIT1(ditch DIT2) is designed in consideration of not only the function ofstopping the spread of the resin leakage but also the ease of removal ofthe resin RS entering the inside of the ditch DIT1 (ditch DIT2). As aresult, in the present embodiment, the depth d2 of the ditch DIT1 (ditchDIT2) is configured so as to be ½ or less of the thickness t1 of thechip mounting portion TAB in order to improve the removalcharacteristics of the entering resin RS.

It is also possible to represent the second feature in the presentembodiment in another expression as shown below. Namely, for example, itcan also be said that the ditch DIT1 (ditch DIT2) is configured so thatthe depth d2 of ditch DIT1 (ditch DIT2) is smaller than the differencein level d1 of the step portion DL as shown in FIG. 8. Thus, accordingto the present embodiment, the depth d2 of the ditch DIT1 (ditch DIT2)can be made shallower. This means that the resin RS entering the insideof the ditch DIT1 (ditch DIT2) can be easily removed. As a result,according to the second feature in the present embodiment, the resin RSentering the ditch DIT1 (ditch DIT2) can be reliably removed by thecleaning process for cleaning the lower surface of the chip mountingportion TAB.

Namely, the resin RS is embedded in the step portion DL, and the removalof the embedded resin RS is not premised. On the other hand, the ditchDIT1 (ditch DIT2) is premised to remove the entering resin RS.Therefore, the step portion DL and the ditch DIT1 (ditch DIT2) differ asto whether to remove the resin RS or not, and since the resin RS can beremoved more easily when the depth becomes shallower, the depth d2 ofthe ditch DIT1 (ditch DIT2) is configured so as to be smaller than thedifference in level d1 of the step portion DL in the present embodiment.

In this regard, in the related technique, for example, the depth of theditch DIT is almost the same as the difference in level of the stepportion DL as shown in FIG. 3. This is because since the relatedtechnique is not based on the premise that the resin RS entering theinside of the ditch DIT is removed, the focus is placed only onimproving the effect of stopping the spread of the resin leakage byincreasing the internal volume of the ditch DIT as much as possible. Onthe other hand, since the present embodiment is based on the premisethat the resin RS entering the inside of the ditch DIT1 (ditch DIT2) isremoved, the depth d2 of the ditch DIT1 (ditch DIT2) is smaller than thedifference in level of the step portion DL in which the removal of theembedded resin RS is not premised as shown in FIG. 8.

As the further devised point of the second feature in the presentembodiment, for example, the shape of the ditch DIT1 and the shape ofthe ditch DIT2 are V-shape as shown in FIG. 8. In this manner, accordingto the present embodiment, the ease of removal of the resin RS enteringthe ditch DIT1 (ditch DIT2) can be improved. This is because since theV-shaped ditch DIT1 (ditch DIT2) in the present embodiment has smallervolume than the semicircular ditch DIT in the related technique shown inFIG. 3 even when the ditch DIT1 (DIT2) has the same depth and width asthose of the semicircular ditch DIT, it considered that the ease ofremoval of the resin RS entering the ditch DIT1 (ditch DIT2) isimproved.

It should be noted that a press method can be used for forming theV-shaped ditch DIT1 (ditch DIT2). Accordingly, the second feature in thepresent embodiment specifically has the first devised point that thedepth d2 of the ditch DIT1 (ditch DIT2) is made shallower and the seconddevised point that the ditch DIT1 (ditch DIT2) is made to have a V-shapeto reduce the volume. Thus, according to the present embodiment, theremoval characteristics of the resin RS entering the ditch DIT1 (ditchDIT2) can be greatly improved by the synergy effect of the first devisedpoint and the second devised point.

Next, the third feature in the present embodiment is that a plurality ofditches (for example, the ditch DIT1 and the ditch DIT2) are provided onthe lower surface of the chip mounting portion TAB as shown in FIGS. 7and 8. This configuration is useful because the ditch DIT1 in thepresent embodiment is premised to remove the resin RS entering the ditchDIT1 and the ditch DIT1 is designed in consideration of not only thefunction of stopping the spread of the resin leakage but also the easeof removal of the resin RS entering the inside of the ditch DIT1.Namely, in the present embodiment, the ease of removal of the resin RSentering the inside of the ditch DIT1 is taken into consideration, andthe second feature described above is made from the viewpoint ofimproving the ease of removal of the resin RS. Further, according to thesecond feature in the present embodiment, the ease of removal of theresin RS entering the ditch DIT1 can be improved by the first devisedpoint that the depth d2 of the ditch DIT1 is made shallower and thesecond devised point that the ditch is made to have a V-shape to reducethe volume. Meanwhile, it can be said that the fact that the ease ofremoval of the resin RS entering the ditch DIT1 can be improvedconversely means that the function of stopping the spread with the ditchDIT1 is reduced. Therefore, in the present embodiment, in order tosuppress the deterioration of the function of stopping the spread, whichappears as a side effect of the configuration for improving the ease ofremoval of the resin RS entering the ditch DIT1, a plurality of ditches(for example, ditch DIT1 and ditch DIT2) are provided on the lowersurface of the chip mounting portion TAB (third feature). In thismanner, for example, the resin RS that cannot be stopped by the ditchDIT1 can be stopped by the ditch DIT2 provided on the inner side of theditch DIT1 as shown in FIG. 18. In other words, according to the thirdfeature in the present embodiment, the function of stopping the spreadcan be fully implemented by suppressing the side effect of the secondfeature of the decrease in the function of stopping the spread.

As described above, according to the present embodiment, the improvementin the function of stopping the spread of the resin leakage on the lowersurface of the chip mounting portion TAB and the improvement in the easeof removal of the resin RS entering the inside of the ditch DIT1 (ditchDIT2) can achieved at a higher level by combining the second feature andthe third feature described above.

The third feature in the present embodiment provides the usefulconfiguration because it is based on the premise of the first featurethat the resin RS entering the inside of the ditch DIT1 (ditch DIT2) isremoved by cleaning the lower surface of the chip mounting portion TAB.This point will be described below.

For example, in the related technique shown in FIG. 3, the removal ofthe resin RS embedded in the ditch DIT is not premised. Therefore, inthe related technique, it is difficult to adopt a plurality of ditchesDIT arranged to be spaced apart from each other on the lower surface ofthe chip mounting portion TAB. This is because when a plurality ofditches DIT are provided on the lower surface of the chip mountingportion TAB in the related technique, the resin RS remains in the regionup to the inner ditch DIT. In other words, when a plurality of ditchesDIT are provided on the lower surface of the chip mounting portion TABto improve the function of stopping the spread of the resin leakage inthe related technique, since the resin RS leaked onto the lower surfaceof the chip mounting portion TAB remains as it is, the region where theresin RS remains increases. This means that the connection reliabilitybetween the semiconductor device and the mounting board is deterioratedand the heat radiation characteristics of the semiconductor device aredeteriorated. Therefore, in the related technique, it is difficult toadopt the configuration in which a plurality of ditches DIT are providedon the lower surface of the chip mounting portion TAB from the viewpointof improving the connection reliability between the semiconductor deviceand the mounting board and improving the heat radiation characteristicsof the semiconductor device. Namely, in the related technique where theremoval of the resin RS embedded in the ditch DIT is not premised, theconfiguration where a single ditch DIT is provided and the internalvolume of the single ditch DIT is increased as much as possible toimprove the effect of stopping the spread of the resin leakage is moreuseful than the configuration where a plurality of ditches DIT areprovided on the lower surface of the chip mounting portion TAB toimprove the effect of stopping the spread of the resin leakage.

On the other hand, the present embodiment is based on the premise thatthe lower surface of the chip mounting portion TAB is cleaned to removethe resin RS entering the inside of the ditch DIT1 (ditch DIT2). In thiscase, since the resin RS entering each of the ditch DIT1 and the ditchDIT2 is removed, the configuration in which a plurality of ditches DIT1and DIT2 are provided does not cause the deterioration of the connectionreliability between the semiconductor device and the mounting board andthe deterioration of the heat radiation characteristics of thesemiconductor device, and the function of stopping the spread of theresin leakage can be improved unlike the related technique. Meanwhile,since the configuration where a single ditch is provided and theinternal volume of the single ditch is increased as much as possible toimprove the effect of stopping the spread of the resin leakagesignificantly lowers the ease of removal of the entering resin RS in thepresent embodiment, it is difficult to adopt the configuration in thepresent embodiment. Here, the present embodiment is based on the premisethat the resin RS entering the inside of the ditch DIT1 (ditch DIT2) isremoved by cleaning the lower surface of the chip mounting portion TAB.Therefore, the configuration where a plurality of ditches (ditch DIT1and ditch DIT2) are provided on the lower surface of the chip mountingportion TAB to improve the function of stopping the spread of the resinleakage is more useful in the present embodiment than the configurationwhere a single ditch DIT is provided on the lower surface of the chipmounting portion TAB and the internal volume of the single ditch DIT isincreased as much as possible to improve the effect of stopping thespread of the resin leakage.

As described above, the present embodiment is different in theorientation (viewpoint) from the related technique. For this reason, thethird feature in the present embodiment that a plurality of ditches(ditch DIT1 and ditch DIT2) spaced apart from each other are provided onthe lower surface of the chip mounting portion TAB has a usefultechnical significance because it is based on the premise of the firstfeature that the lower surface of the chip mounting portion TAB iscleaned to remove the resin RS entering the inside of the ditch DIT1(ditch DIT2).

Subsequently, the fourth feature in the present embodiment is that thedevise of suppressing the entry of the resin RS as much as possible isprovided at the outer peripheral portion of the lower surface of thechip mounting portion TAB. This is because if the entry of the resin RScan be suppressed at the outer peripheral portion of the lower surfaceof the chip mounting portion TAB as much as possible, the area where theresin RS enters can be reduced in the lower surface of the chip mountingportion TAB, so that the ease of removal of the resin RS entering thelower surface can be improved.

The specific first devised point of the fourth feature in the presentembodiment is that the distance L1 between the step portion DL and thecenter position of the ditch DIT1 is smaller than the distance L2between the center position of the ditch DIT1 and the center position ofthe ditch DIT2 in a cross-sectional view as shown in FIG. 8. This allowsthe arrangement position of the ditch DIT1 arranged on the outside toapproach the outer peripheral portion of the chip mounting portion TAB.Namely, the area of the resin RS entering the lower surface of the chipmounting portion TAB can be reduced as the arrangement position of theditch DIT1 arranged on the outside is closer to the outer peripheralportion of the chip mounting portion TAB. Thus, according to the fourthfeature in the present embodiment, the ease of removal of the resin RSentering the lower surface of the chip mounting portion TAB can beimproved.

Next, the further specific second devised point of the fourth feature inthe present embodiment is that the ditch DIT1 (ditch DIT2) arranged toextend along the outer peripheral portion of the lower surface of thechip mounting portion TAB has a tapered shape near the corner portion ofthe chip mounting portion TAB as shown in FIG. 7. In other words, thechip mounting portion TAB has a first side extending in the firstdirection, a second side crossing the first side, and a corner portionwhich is the intersection of the first side and the second side.

Further, the ditch DIT1 (ditch DIT2) includes a first portion parallelto the first side, a second portion parallel to the second side, and athird portion connecting the first portion and the second portion. Here,the distance between the third portion of the ditch DIT1 (ditch DIT2)and the corner portion is longer than the distance between the firstportion of the ditch DIT1 (ditch DIT2) and the first side, and is longerthan the distance between the second portion of the ditch DIT1 (ditchDIT2) and the second side. In particular, the angle formed by the thirdportion and the first portion is an obtuse angle, and the angle formedby the third portion and the second portion is also an obtuse angle.

Thus, according to the further specific second devised point of thefourth feature in the present embodiment, the ditch DIT1 (ditch DIT2)can be arranged as close as possible to the vicinity of the outerperipheral portion of the chip mounting portion TAB. This is becausealthough the ditch DIT1 (ditch DIT2) must be separated from the cornerportion of the chip mounting portion TAB by a certain distance due tothe design layout constraint, the presence of the tapered shape makes itpossible to arrange the ditch DIT1 (ditch DIT2) as close as possible tothe vicinity of the outer peripheral portion of the chip mountingportion TAB while securing the distance between the corner portion andthe tapered shape as compared with the case where the tapered shape isnot present. As a result, according to the present embodiment, the areaof resin RS entering the lower surface of the chip mounting portion TABcan be reduced, and thus the ease of removal of the resin RS enteringthe lower surface of the chip mounting portion TAB can be improved.

From the foregoing, according to the fourth feature in the presentembodiment, the ditch DIT1 (ditch DIT2) can be arranged as close aspossible to the vicinity of the outer peripheral portion of the chipmounting portion TAB by the synergy effect of the first devised pointand the second devised point. As a result, the amount of the resin RSentering the lower surface of the chip mounting portion TAB can bereduced, and thus the ease of removal of the resin RS entering the lowersurface of the chip mounting portion TAB can be greatly improved.

Next, the fifth feature in the present embodiment is that the differencein level d1 of the step portion DL is ½ or less of the thickness t1 ofthe chip mounting portion TAB as shown in FIG. 8. Here, from theviewpoint of effectively suppressing the entry of the resin RS onto thelower surface of the chip mounting portion TAB, it can be thought thatit is desirable that the difference in level of the step portion DL islarge. From this point, for example, it can be thought that it isdesirable that the difference in level of the step portion DL is largerthan ½ of the thickness of the chip mounting portion TAB as in therelated technique shown in FIG. 3. However, in the present embodiment,the difference in level d1 of the step portion DL is set to ½ or less ofthe thickness t1 of the chip mounting portion TAB.

This is for the following reason. That is, the step portion DL is formedby, for example, a press method, and the amount of crushing increases asthe difference in level of the step portion DL increases, so that theflatness of the upper surface of the chip mounting portion TAB isdeteriorated. Further, the deterioration in the flatness of the uppersurface of the chip mounting portion TAB leads to the deterioration inthe mountability of the semiconductor chip CHP mounted on the uppersurface of the chip mounting portion TAB. Therefore, in the presentembodiment, the difference in level d1 of the step portion DL is set to½ or less of the thickness t1 of the chip mounting portion TAB. In thiscase, since the amount of crushing when the step portion DL is formed bythe press method can be reduced, the deterioration in the flatness ofthe upper surface of the chip mounting portion TAB can be suppressed.Therefore, according to the fifth feature in the present embodiment, thedeterioration in the mountability of the semiconductor chip CHP mountedon the upper surface of the chip mounting portion TAB can be suppressed.

Further, according to the fifth feature in the present embodiment, theeffect of suppressing the entry of the resin RS onto the lower surfaceof the chip mounting portion TAB with the single step portion DL isreduced. However, according to the present embodiment, since the ditchDIT1 is provided on the inner side of the step portion DL and the ditchDIT2 is provided on the inner side of the ditch DIT1, the entry of theresin RS onto the lower surface of the chip mounting portion TAB can besufficiently suppressed by the combination of the step portion DL, theditch DIT1, and the ditch DIT2. In other words, since the entry of theresin RS onto the lower surface of the chip mounting portion TAB issuppressed to a minimum by the combination of the step portion DL, theditch DIT1, and the ditch DIT2, it is further useful to adopt the fifthfeature in the present embodiment from the viewpoint of improving theflatness of the upper surface of the chip mounting portion TAB.

First Modification Example

FIG. 23A is an enlarged view showing a part of the chip mounting portionTAB in the first modification example. As shown in FIG. 23A, on thelower surface of the chip mounting portion TAB in the first modificationexample, the step portion DL is provided at the outer end, the ditchDIT1 is formed on the inner side of the step portion DL so as to bespaced apart from the step portion DL, and the ditch DIT2 is formed onthe inner side of the ditch DIT1 so as to be spaced apart from the ditchDIT1.

Here, in this first modification example, the depth of the ditch DIT1 isdifferent from the depth of the ditch DIT2. Specifically, the depth ofthe ditch DIT1 is deeper than the depth of the ditch DIT2. In otherwords, the depth of the ditch DIT2 is shallower than the depth of theditch DIT1. More specifically, as shown in FIG. 23A, the relationshipd1>d2 a>d2 b holds between the difference in level d1 of the stepportion DL, the depth d2 a of the ditch DIT1, and the depth d2 b of theditch DIT2.

This is for the following reason. That is, the resin is embedded in thestep portion DL, and the removal of the resin embedded in the stepportion DL is not premised. On the other hand, the ditch DIT1 (ditchDIT2) is premised to remove the entering resin. Accordingly, the stepportion DL and the ditch DIT1 (ditch DIT2) differ as to whether toremove the resin or not, and since the resin can be more easily removedwhen the depth is shallower, the depth d2 a of the ditch DIT1 and thedepth d2 b of the ditch DIT2 are smaller than the difference in level d1of the step portion DL also in this first modification example.

Furthermore, in this first modification example, the following point isalso taken into consideration. For example, when the resin RS enters theditch DIT1 and the ditch DIT2 formed on the lower surface of the chipmounting portion TAB as shown in FIG. 18, the amount of the resin RSentering the ditch DIT1 is larger than the amount of the resin RSentering the ditch DIT2. In other words, the entry of the resin RS isfirst suppressed by the ditch DIT1 formed on the outside, and the resinRS that cannot be stopped by the ditch DIT1 is stopped by the ditch DIT2formed on the inside. Accordingly, as shown in FIG. 18, the amount ofthe resin RS entering the ditch DIT1 is larger than the amount of theresin RS entering the ditch DIT2. Therefore, in this first modificationexample, the depth d2 a of the ditch DIT1 is made deeper than the depthd2 b of the ditch DIT2. Thus, according to this first modificationexample, since the depth d2 a of the ditch DIT1 arranged on the outsideis smaller than the difference in level d1 of the step portion DL, theease of removal can be secured, and the function of stopping the spreadis sufficiently secured by making the depth d2 a of the ditch DIT1deeper than the depth d2 b of the ditch DIT2. In other words, accordingto this first modification example, since the ditch DIT2 arranged on theinside is not required to have the effect of stopping the spread of theresin as compared with the ditch DIT1, the ease of removal of the resinis improved by making the depth d2 b of the ditch DIT2 shallower thanthe depth d2 a of the ditch DIT1.

Second Modification Example

FIG. 23B is an enlarged view showing a part of the chip mounting portionTAB in the second modification example. As shown in FIG. 23B, on thelower surface of the chip mounting portion TAB in the secondmodification example, the step portion DL is provided at the outer end,the ditch DIT1 is formed on the inner side of the step portion DL so asto be spaced apart from the step portion DL, and the ditch DIT2 isformed on the inner side of the ditch DIT1 so as to be spaced apart fromthe ditch DIT1.

Here, in this second modification example, the shape of the ditch DIT1and the shape of the ditch DIT2 are semicircular. In other words,although the example in which the ditch DIT1 and the shape of the ditchDIT2 are formed to have the V shape as shown in FIG. 8 has beendescribed in the embodiment, the shape of the ditch DIT1 and the shapeof the ditch DIT2 are not limited to this, and the ditch DIT1 and theditch DIT2 may be formed to have a semicircular shape as in the secondmodification example shown in FIG. 23B. In this case, for example, sincethe ditch DIT1 and ditch DIT2 can be formed by etching process, theamount of crushing as in the press method does not occur, and theadvantage that the flatness of the upper surface of the chip mountingportion TAB can be easily secured can be obtained.

Third Modification Example

Although the QFP has been described in the embodiment as an example ofthe package configuration of the semiconductor device PKG1, thetechnical idea in the embodiment can be applied also to a semiconductordevice adopting the QFN (Quad Flat Non-Leaded Package) as the packageconfiguration other than the semiconductor device adopting the QFP.

(Individual Molding Type)

FIG. 24A is an external view of the semiconductor device PKG2 in thisthird modification example viewed from the upper surface side, and FIG.24B is an external view of the semiconductor device PKG2 in this thirdmodification example viewed from the lower surface side. As shown inFIG. 24B, a plurality of leads LD are arranged in the outer peripheralportion of the lower surface of the sealing body MR, and the lowersurface of the chip mounting portion TAB is exposed from the sealingbody MR in the central part of the lower surface of the sealing body MR.Further, the ditch DIT1 and the ditch DIT2 are formed on the exposedlower surface of the chip mounting portion TAB.

FIG. 25 is a cross-sectional view showing the semiconductor device PKG2in this third modification example. As shown in FIG. 25, it can be seenthat the ditch DIT1 and the ditch DIT2 are formed on the lower surfaceof the chip mounting portion TAB exposed from the sealing body MR alsoin the semiconductor device PKG2 in this third modification example. Inthis manner, the technical idea in the embodiment can be embodied alsoin the semiconductor device PKG2 in this third modification example.

(Batch Molding Type)

FIG. 26A is an external view of the semiconductor device PKG3 in thisthird modification example viewed from the upper surface side, and FIG.26B is an external view of the semiconductor device PKG3 in this thirdmodification example viewed from the lower surface side. As shown inFIG. 26B, a plurality of leads LD are arranged in the outer peripheralportion of the lower surface of the sealing body MR, and the lowersurface of the chip mounting portion TAB is exposed from the sealingbody MR in the central part of the lower surface of the sealing body MR.Further, the ditch DIT1 and the ditch DIT2 are formed on the exposedlower surface of the chip mounting portion TAB.

FIG. 27 is a cross-sectional view showing the semiconductor device PKG3in this third modification example. As shown in FIG. 27, it can be seenthat the ditch DIT1 and the ditch DIT2 are formed on the lower surfaceof the chip mounting portion TAB exposed from the sealing body MR alsoin the semiconductor device PKG3 in this third modification example. Inthis manner, the technical idea in the embodiment can be embodied alsoin the semiconductor device PKG3 in this third modification example.

In the foregoing, the invention made by the inventor of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

The embodiment described above includes the following modes.

(Appendix 1)

A semiconductor device comprising:

a chip mounting portion having a lower surface on which a first ditch isformed;

a semiconductor chip mounted on an upper surface of the chip mountingportion;

a lead electrically connected to a pad of the semiconductor chip througha conductive member; and

a sealing body configured to seal the semiconductor chip,

wherein the lower surface of the chip mounting portion is exposed fromthe sealing body, and

wherein a plating film is formed on the lower surface including aninside of the first ditch.

(Appendix 2)

The semiconductor device according to appendix 1,

wherein resin constituting the sealing body is not formed inside thefirst ditch.

(Appendix 3)

The semiconductor device according to appendix 1,

wherein the first ditch is formed along an outer peripheral portion ofthe chip mounting portion.

(Appendix 4)

The semiconductor device according to appendix 1,

wherein a depth of the first ditch is ½ or less of a thickness of thechip mounting portion.

(Appendix 5)

The semiconductor device according to appendix 1,

wherein the first ditch has a V-shaped cross section.

(Appendix 6)

The semiconductor device according to appendix 1,

wherein a second ditch is further formed on the lower surface of thechip mounting portion so as to be spaced apart from the first ditch.

(Appendix 7)

The semiconductor device according to appendix 6,

wherein the second ditch is formed on an inner side of the chip mountingportion relative to the first ditch.

(Appendix 8)

The semiconductor device according to appendix 6,

wherein a depth of the first ditch and a depth of the second ditch areboth ½ or less of a thickness of the chip mounting portion.

(Appendix 9)

The semiconductor device according to appendix 7,

wherein a depth of the first ditch is deeper than a depth of the secondditch.

(Appendix 10)

The semiconductor device according to appendix 6,

wherein the plating film is formed also on an inner wall of the secondditch.

(Appendix 11)

The semiconductor device according to appendix 6,

wherein resin constituting the sealing body is not formed inside thesecond ditch.

(Appendix 12)

The semiconductor device according to appendix 1,

wherein a step portion spaced apart from the first ditch is formed at anouter end of the lower surface of the chip mounting portion.

(Appendix 13)

The semiconductor device according to appendix 12,

wherein the first ditch is formed on an inner side of the step portion.

(Appendix 14)

The semiconductor device according to appendix 12,

wherein a depth of the first ditch is shallower than a difference inlevel of the step portion.

(Appendix 15)

The semiconductor device according to appendix 12,

wherein a second ditch is formed on an inner side of the first ditch onthe lower surface of the chip mounting portion, and

a distance between the step portion and a center position of the firstditch is smaller than a distance between the center position of thefirst ditch and a center position of the second ditch in across-sectional view.

(Appendix 16)

The semiconductor device according to appendix 12,

wherein resin constituting the sealing body is formed inside the stepportion.

(Appendix 17)

The semiconductor device according to appendix 1,

wherein the chip mounting portion has a first side extending in a firstdirection, a second side crossing the first side, and a corner portionwhich is an intersection of the first side and the second side,

wherein the first ditch includes a first portion parallel to the firstside, a second portion parallel to the second side, and a third portionconnecting the first portion and the second portion, and

wherein a distance between the third portion of the first ditch and thecorner portion is longer than a distance between the first portion ofthe first ditch and the first side, and is longer than a distancebetween the second portion of the first ditch and the second side.

(Appendix 18)

The semiconductor device according to appendix 17,

wherein an angle formed by the third portion and the first portion is anobtuse angle, and

wherein an angle formed by the third portion and the second portion isan obtuse angle.

REFERENCE SIGNS LIST

-   CHP semiconductor chip-   DIT1 ditch-   DIT2 ditch-   DL step portion-   LD lead-   LF lead frame-   MR sealing body-   PF plating film-   RS resin-   TAB chip mounting portion-   W wire

1. A semiconductor device comprising: a chip mounting portion having alower surface on which a first ditch is formed; a semiconductor chipmounted on an upper surface of the chip mounting portion; a leadelectrically connected to a pad of the semiconductor chip through aconductive member; and a sealing body configured to seal thesemiconductor chip, wherein the lower surface of the chip mountingportion is exposed from the sealing body, and wherein a plating film isformed on the lower surface including an inside of the first ditch. 2.The semiconductor device according to claim 1, wherein resinconstituting the sealing body is not formed inside the first ditch. 3.The semiconductor device according to claim 1, wherein the first ditchis formed along an outer peripheral portion of the chip mountingportion.
 4. The semiconductor device according to claim 1, wherein adepth of the first ditch is ½ or less of a thickness of the chipmounting portion.
 5. The semiconductor device according to claim 1,wherein the first ditch has a V-shaped cross section.
 6. Thesemiconductor device according to claim 1, wherein a second ditch isfurther formed on the lower surface of the chip mounting portion so asto be spaced apart from the first ditch.
 7. The semiconductor deviceaccording to claim 6, wherein the second ditch is formed on an innerside of the chip mounting portion relative to the first ditch.
 8. Thesemiconductor device according to claim 6, wherein a depth of the firstditch and a depth of the second ditch are both ½ or less of a thicknessof the chip mounting portion.
 9. The semiconductor device according toclaim 7, wherein a depth of the first ditch is deeper than a depth ofthe second ditch.
 10. The semiconductor device according to claim 6,wherein the plating film is formed also on an inner wall of the secondditch.
 11. The semiconductor device according to claim 6, wherein resinconstituting the sealing body is not formed inside the second ditch. 12.The semiconductor device according to claim 1, wherein a step portionspaced apart from the first ditch is formed at an outer end of the lowersurface of the chip mounting portion.
 13. The semiconductor deviceaccording to claim 12, wherein the first ditch is formed on an innerside of the step portion.
 14. The semiconductor device according toclaim 12, wherein a depth of the first ditch is shallower than adifference in level of the step portion.
 15. The semiconductor deviceaccording to claim 12, wherein a second ditch is formed on an inner sideof the first ditch on the lower surface of the chip mounting portion,and a distance between the step portion and a center position of thefirst ditch is smaller than a distance between the center position ofthe first ditch and a center position of the second ditch in across-sectional view.
 16. The semiconductor device according to claim12, wherein resin constituting the sealing body is formed inside thestep portion.
 17. The semiconductor device according to claim 1, whereinthe chip mounting portion has a first side extending in a firstdirection, a second side crossing the first side, and a corner portionwhich is an intersection of the first side and the second side, whereinthe first ditch includes a first portion parallel to the first side, asecond portion parallel to the second side, and a third portionconnecting the first portion and the second portion, and wherein adistance between the third portion of the first ditch and the cornerportion is longer than a distance between the first portion of the firstditch and the first side, and is longer than a distance between thesecond portion of the first ditch and the second side.
 18. Thesemiconductor device according to claim 17, wherein an angle formed bythe third portion and the first portion is an obtuse angle, and whereinan angle formed by the third portion and the second portion is an obtuseangle.